1. Field of the Invention
The present invention relates to a diagnosis method, particularly to a defect diagnosis method for implementation in semiconductor fab, flat panel display fab, solar cell fab, Printed Circuit Board (PCB) mask fab or LED assembly house.
2. Description of Related Art
The sophisticated manufacturing techniques in a fabrication process for integrated circuit dice includes film deposition, masking, photo lithography, etching, etc. During the fabrication process, defects may occur as a result of factors attributed from different sources, for example, equipment malfunction, facility leak, impurities of environment, and design layout problems or the like. These defects can generally be categorized into random defects or systematic defects. Regardless of the form of defect, defects in pattern size may affect the production yield, which in turn will translate into higher cost. In a fab (i.e. manufacturing factory), “Perform defect and image pattern metrology data analysis real time in manufacturing stage” becomes a key approach to yield enhancement and core innovation in this article.
First, we can perform defect data mining with automatic defect classification, killer defect (i.e. defect of material or device layout which is a reason for the catastrophic failure of the device) yield and pattern contour metrology data of all fab SEM (scanning electron microscope) and optical images, (reference is made to patent Ser. No. 12/318,974 automatic defect yield diagnosis system by the instant Applicant), fab in-line data, and Cp (Chip probe) yield test data. Current manual defect image review operations can not provide defect data mining techniques in defect analysis because of insufficient defect analysis data. So, defect data mining using information in the fab in-line data (which may include critical dimension, thickness, lot history, equipment run history, Fault Detection and Classification/FDC data, etc.), 100% automatic defect classification and killer defect yield, Cp test binning data, and all image (SEM or optical images) pattern contour metrology data analysis system, will offer innovative and quick solution to defect yield.
Second, the integration of all process steps' defect yield prediction data and product logistic WIP (Work-in-Process) data provides fab and design house not just the wafer quantity delivery data, but also good die delivery quantities prediction real time.
Third, the cumulative frequent failure defect layout pattern analysis across lots and products can be achieved through “Layout based defect composite pattern group” method (according to previous invention “Method for Smart defect screen and sample”). Defect pattern library collects those frequent failure defect layout pattern for Design-for-manufacturing (DFM) check and yield improvement.
Last, layout, and lithography simulation (ex. Optical Proximity Correction simulation) pattern analysis with all fab image pattern contours are composite overlapped with pattern match. Pattern contour metrology data are checked against layout pattern spec to identify systematic defect pattern and process defect pattern. The defect layout pattern can be from either mapping layout pattern of corresponding defect image pattern or pre-extracted design weak layout patterns of interest in Graphic Database System (GDS) or in Open Access Same-time Information System (OASIS). Those systematic defect or process defect layout pattern are saved in defect pattern library for DFM check and yield improvement.
Consequently, because of the above consideration resulting from the technical design of prior art, the inventor strives via real world experience and academic research to develop the present invention, which can effectively improve the limitations described above.